NAMD: CudaComputeNonbonded.h Source File

00001 #ifndef CUDACOMPUTENONBONDED_H
00002 #define CUDACOMPUTENONBONDED_H
00003 #include <vector>
00004 #include "Compute.h"
00005 #include "Box.h"
00006 #include "PatchTypes.h"
00007 #include "CudaUtils.h"
00008 #include "ComputeNonbondedUtil.h"
00009 #include "CudaNonbondedTables.h"
00010 #include "CudaTileListKernel.h"
00011 #include "CudaComputeNonbondedKernel.h"
00012 #include "CudaComputeGBISKernel.h"
00013 #include "ComputeMgr.h"
00014 #ifdef NAMD_CUDA
00015 #include <cuda.h>
00016 
00017 // 2^11 ints * 2^5 bits = 2^16 bits = range of unsigned short excl_index
00018 // 2^27 ints * 2^5 bits = 2^32 bits = range of unsigned int excl_index
00019 #define MAX_EXCLUSIONS (1<<27)
00020 
00021 class CudaComputeNonbonded : public Compute, public ComputeNonbondedUtil {
00022 public:
00023   struct ComputeRecord {
00024     ComputeID cid;
00025     PatchID pid[2];
00026     // Index to patches[] -array
00027     int patchInd[2];
00028     Vector offset;
00029   };
00030 
00031   struct PatchRecord {
00032     PatchRecord(PatchID patchID) : patchID(patchID) {
00033       patch = NULL;
00034       compAtom = NULL;
00035       results = NULL;
00036       positionBox = NULL;
00037       forceBox = NULL;
00038       intRadBox = NULL;
00039       psiSumBox = NULL;
00040       bornRadBox = NULL;
00041       dEdaSumBox = NULL;
00042       dHdrPrefixBox = NULL;
00043     }
00044     PatchID patchID;
00045     Patch *patch;
00046     int numAtoms;
00047     int numFreeAtoms;
00048     int atomStart;
00049     // Pe where the patch was registered
00050     int pe;
00051     // For priority sorting
00052     int reversePriorityRankInPe;
00053     bool isSamePhysicalNode;
00054     bool isSameNode;
00055     // Storage for open positionBox
00056     CompAtom *compAtom;
00057     // Storage for open forceBox
00058     Results *results;
00059     // Boxes
00060     Box<Patch,CompAtom> *positionBox;
00061     Box<Patch,Results> *forceBox;
00062     Box<Patch,Real>   *intRadBox; //5 GBIS Boxes
00063     Box<Patch,GBReal> *psiSumBox;
00064     Box<Patch,Real>   *bornRadBox;
00065     Box<Patch,GBReal> *dEdaSumBox;
00066     Box<Patch,Real>   *dHdrPrefixBox;
00067     Real   *intRad; //5 GBIS arrays
00068     GBReal *psiSum;
00069     Real   *bornRad;
00070     GBReal *dEdaSum;
00071     Real   *dHdrPrefix;
00072     bool operator < (const PatchRecord& pr) const {
00073       return (patchID < pr.patchID);
00074     }
00075     bool operator == (const PatchRecord& pr) const {
00076       return (patchID == pr.patchID);
00077     }
00078   };
00079 
00080 private:
00081   // This variable is set in atomUpdate() by any Pe
00082   bool atomsChangedIn;
00083   // This variable is set in doWork() by masterPe
00084   bool atomsChanged;
00085 
00086   bool computesChanged;
00087 
00088   const int deviceID;
00089   size_t maxShmemPerBlock;
00090   cudaStream_t stream;
00091 
00092   // PME and VdW CUDA kernels
00093   CudaComputeNonbondedKernel nonbondedKernel;
00094 
00095   // GBIS kernel
00096   CudaComputeGBISKernel GBISKernel;
00097 
00098   // Tile list CUDA kernels
00099   CudaTileListKernel tileListKernel;
00100 
00101   // Exclusions
00102   int2 *exclusionsByAtom;
00103 
00104   // VdW-types
00105   // Pinned host memory
00106   int* vdwTypes;
00107   int vdwTypesSize;
00108 
00109   // Maximum number of tiles per tile list
00110   int maxTileListLen;
00111 
00112   // Pinned host memory
00113   int2* exclIndexMaxDiff;
00114   int exclIndexMaxDiffSize;
00115 
00116   // Pinned host memory
00117   int* atomIndex;
00118   int atomIndexSize;
00119 
00120   // Required (xyzq, vdwTypes) storage
00121         int atomStorageSize;
00122 
00123   // Atom and charge storage
00124   // Pinned host memory
00125   CudaAtom* atoms;
00126   int atomsSize;
00127 
00128   // Force storage
00129   float4* h_forces;
00130   int h_forcesSize;
00131   float4* h_forcesSlow;
00132   int h_forcesSlowSize;
00133 
00134   float4* d_forces;
00135   int d_forcesSize;
00136   float4* d_forcesSlow;
00137   int d_forcesSlowSize;
00138 
00139   // Virial and energy storage
00140   VirialEnergy* h_virialEnergy;
00141   VirialEnergy* d_virialEnergy;
00142 
00143   // GBIS storage
00144   //--------------
00145   // Pinned host memory
00146   float* intRad0H;
00147   int intRad0HSize;
00148   // Pinned host memory
00149   float* intRadSH;
00150   int intRadSHSize;
00151   // Mapped host memory
00152   GBReal* psiSumH;
00153   int psiSumHSize;
00154   // Pinned host memory
00155   float* bornRadH;
00156   int bornRadHSize;
00157   // Mapped host memory
00158   GBReal* dEdaSumH;
00159   int dEdaSumHSize;
00160   // Pinned host memory
00161   float* dHdrPrefixH;
00162   int dHdrPrefixHSize;
00163 
00164   // Event and sanity check flag for making sure event was actually recorded
00165   cudaEvent_t forceDoneEvent;
00166   bool forceDoneEventRecord;
00167   // Check counter for event polling
00168   int checkCount;
00169 
00170   // Node lock
00171   CmiNodeLock lock;
00172   // List of local PEs that have patches
00173   std::vector<int> pes;
00174   // List of patch indices on each rank
00175   std::vector< std::vector<int> > rankPatches;
00176   // Master Pe = Pe where this Compute and reduction lives
00177   int masterPe;
00178 
00179   // Are we in skip?
00180   bool doSkip;
00181 
00182   // Device-wide patch and compute records, and the list of patches
00183   std::vector<ComputeRecord> computes;
00184   std::vector<PatchRecord> patches;
00185 
00186   // CUDA versions of patches
00187   // Pinned host memory
00188   CudaPatchRecord* cudaPatches;
00189 
00190   SubmitReduction *reduction;
00191 
00192   // Pair lists
00193   int pairlistsValid;
00194   float pairlistTolerance;
00195   int usePairlists;
00196   int savePairlists;
00197   float plcutoff2;
00198 
00199   bool reSortDone;
00200 
00201   // Flags
00202   bool doSlow;
00203   bool doEnergy;
00204   bool doVirial;
00205 
00206   // Walltime for force compute start
00207   double beforeForceCompute;
00208 
00209   static inline void updateVdwTypesExclLoop(int first, int last, void *result, int paraNum, void *param);
00210   void updateVdwTypesExclSubset(int first, int last);
00211 
00212   static inline void copyAtomsLoop(int first, int last, void *result, int paraNum, void *param);
00213   void copyAtomsSubset(int first, int last);
00214 
00215   void addPatch(PatchID pid);
00216   void addCompute(ComputeID cid, PatchID pid1, PatchID pid2, Vector offset);
00217   void updatePatches();
00218   int calcNumTileLists();
00219   void getMaxMovementTolerance(float& maxAtomMovement, float& maxPatchTolerance);
00220   void updateVdwTypesExcl();
00221   void buildNeighborlist();
00222   void skip();
00223   void doGBISphase1();
00224   void doGBISphase2();
00225   void doGBISphase3();
00226   void doForce();
00227   void finishSetOfPatchesOnPe(std::vector<int>& patchSet);
00228   void finishPatches();
00229   void finishGBISPhase(int i);
00230   void finishTimers();
00231   void reSortTileLists();
00232   void forceDone();
00233   static void forceDoneCheck(void *arg, double walltime);
00234   void forceDoneSetCallback();
00235   void updateComputes();
00236   void buildExclusions();
00237   void skipPatch(int i);
00238   void openBox(int i);
00239   void reallocateArrays();
00240   void copyGBISphase(int i);
00241   void updatePatch(int i);
00242   int findPid(PatchID pid);
00243   void assignPatch(int i);
00244   ComputeMgr* computeMgr;
00245   int patchesCounter;
00246 
00247   const bool doStreaming;
00248   int* patchReadyQueue;
00249   int patchReadyQueueNext, patchReadyQueueLen;
00250 
00251   void finishPatch(int i);
00252   void unregisterBox(int i);
00253 
00254   // void writeId(const char* filename);
00255   // void writeXYZ(const char* filename);
00256 
00257 public:
00258   CudaComputeNonbonded(ComputeID c, int deviceID, CudaNonbondedTables& cudaNonbondedTables, bool doStreaming);
00259   ~CudaComputeNonbonded();
00260   void registerComputeSelf(ComputeID cid, PatchID pid);
00261   void registerComputePair(ComputeID cid, PatchID* pid, int* trans);
00262   void assignPatches(ComputeMgr* computeMgrIn);
00263   virtual void initialize();
00264   virtual void atomUpdate();
00265   virtual int noWork();
00266   virtual void doWork();
00267   void launchWork();
00268   void finishReductions();
00269   void unregisterBoxesOnPe();
00270   void assignPatchesOnPe();
00271   void openBoxesOnPe();
00272   void skipPatchesOnPe();
00273   void finishPatchesOnPe();
00274   void finishPatchOnPe(int i);
00275   void messageEnqueueWork();
00276   virtual void patchReady(PatchID, int doneMigration, int seq);
00277   virtual void gbisP2PatchReady(PatchID, int seq);
00278   virtual void gbisP3PatchReady(PatchID, int seq);
00279 };
00280 
00281 #endif // NAMD_CUDA
00282 #endif // CUDACOMPUTENONBONDED_H